This invention pertains generally to semiconductor devices and, more particularly, to a nonvolatile memory device and fabrication process.
Electrically programmable read only memory (EPROM) has been widely used as nonvolatile memory which can keep data unchanged even though the power is turned off. However, EPROM devices have a major disadvantage in that they have to be exposed to Ultra-Violet (UV) light for about 20 minutes for data erasure. This is very inconvenient because an EPROM device has to be unplugged from its socket and moved to the UV light source when the data needs to be changed.
Electrically erasable programmable read only memory (EEPROM) overcomes this problem and permits data to be erased electrically in a much shorter period of time, typically less than 2 seconds. However, it still has a disadvantage in that the data must be erased on a byte-by-byte basis.
Flash EEPROM is similar to EEPROM in that data is erased electrically and relatively quickly. However, with flash EEPROM, the data is erased in blocks which typically range in size from 128 to 64K bytes per block, rather than on a byte-by-byte basis.
In general, there are two basic types of nonvolatile memory cell structures: stack-gate and split-gate. The stack-gate memory cell usually has a floating gate and a control gate, with the control gate being positioned directly above the floating gate. In a split-gate cell the control gate is still positioned above the floating gate, but it is offset laterally from it. The fabrication process for a stack-gate cell is generally simpler than that for a split-gate cell. However, a stack-gate cell has an over-erase problem which a split-gate cell does not have. This problem is commonly addressed by maintaining the threshold voltage of the cell in a range of about 0.5-2.0 volts after an erase cycle, which adds complexity to the circuit design.
A split-gate memory cell has an additional gate known as a select gate which avoids the over-erase problem and makes circuit design relatively simple. Such cells are typically fabricated in double-poly or triple-poly processes which are relatively complex, and they are more susceptible to various disturbances during programming and read operations.
EEPROM devices have typically included a stack-gate transistor and a separate select gate transistor. With no over-erase problem, circuit design has been relatively simple, but these devices have a relatively high die cost due to larger cell size as compared to split-gate and stack-gate memory cells.
A memory cell is erased by forcing electrons to migrate away from the floating gate so that it becomes charged with positive ions. This is commonly accomplished by Fowler-Nordheim tunneling in which a tunnel oxide having a thickness on the order of 70-120 xc3x85 is formed between the monocrystalline silicon substrate and the floating gate. A relative strong electric field (greater than 10 mV/cm) is then applied to the tunnel oxide, and the electrons tunnel from the floating gate toward the underlying source, drain or channel region. This technique is widely used both in stack-gate cells and in split-gate cells, and is described in greater detail in U.S. Pat. Nos. 5,792,670, 5,402,371, 5,284,784 and 5,445,792.
Another way of forming an erase path is to grow a dielectric film between two polysilicon (poly-Si) layers as a tunneling dielectric. U.S. Pat. No. 5,029,130 discloses the formation of a sharp edge on the floating gate to enhance the local electric field around it, with the erase path being formed between the sharp edge and the control gate. By adding a third polycrystalline silicon layer as an erase layer which crosses over, or overlies, the floating gate and the control gate, an erase path can be formed between the side wall of floating gate and the erase layer. This technique is disclosed in U.S. Pat. Nos. 5,847,996 and 5,643,812.
Fowler-Nordheim tunneling can also be used to program a memory cell by forcing electrons to tunnel into the floating gate so that it becomes charged negatively. U.S. Pat. Nos. 5,792,670 and 5,402,371 show examples in which electrons are forced to tunnel into the floating gate from the channel region beneath it.
Another way of programming a memory cell is by the use of channel hot carrier injection. During a programming operation, the electrons flowing from the source to the drain are accelerated by a high electric field across the channel region, and some of them become heated near the drain junction. Some of the hot electrons exceed the oxide barrier height and are injected into floating gate. This technique is found in U.S. Pat. No. 4,698,787.
FIG. 1 illustrates a prior art NOR-type flash EEPROM cell array in which the floating gates 16 have end caps 16a, 16b which extend over the adjacent isolation oxide regions 19. The floating gate is typically made of polysilicon or amorphous silicon with a thickness on the order of 1500-2500 xc3x85. Control gates 21 cross over the floating gates, and are typically made of heavily doped polysilicon or polycide. Select gates 22 are separated from and parallel to the control gates. Bit lines 23, which are typically formed by a metallization layer, connect all of the drain of the memory cells in the respective columns, with adjacent ones of the bit lines being isolated from each other. All of the sources of the memory cells in a given row are connected together by a common source line 24 which is typically formed by an N+ or a P+ diffusion layer in the single crystalline silicon substrate.
The floating gate end caps 16a, 16b are required because of a corner-rounding effect or a shift of the floating gate which occurs during the photolithographic step by which the floating gate is formed. The corner-rounding effect may make the edges 16c, 16d of the floating gate shorter, and the shift of the floating gate may make one or both of the edges 16c, 16d move beyond the edges 28a, 28b of active area 28. Both of these effects can cause malfunction of the memory cell because a leakage path may occur when the floating gate does not completely cover the active area or its channel length becomes too short.
FIGS. 2A and 2B illustrate the memory cell array of FIG. 1 with shallow trench and LOCOS (local oxidation of silicon) isolation, respectively. As seen in these figures, an inter-poly dielectric film 31 is formed between the conduction layers which form the floating gates 16 and the control gates 21. Those layers are commonly referred to as the poly-1 and poly-2 layers, respectively, and the dielectric film is typically formed of either pure oxide or a combination of oxide and nitride films.
The end caps 16a, 16b which extend over the adjacent isolation oxide regions 19 help in the formation of large capacitance areas between the control gates 21 and the floating gates 16. Consequently, the coupling ratio from the control gate to the floating gate becomes large, and this makes it possible to couple more voltage from the control gate to the floating gate during programming and erase operations. In order to insure that the floating gate will completely cover the active area and that the channel length will not become too short due to variations during the fabrication process, it is necessary to add tolerance to the memory cell layout by making the floating gate caps wider. In addition, the distance 32 between the end caps has to be kept wide enough to avoid shorts from developing between the floating gates. As a result, the size of the memory cell increases, and the cost gets higher.
It is in general an object of the invention to provide a new and improved memory cell and process for fabricating the same.
Another object of the invention is to provide a memory cell and process of the above character which overcome the limitations and disadvantages of the prior art.
These and other objects are achieved in accordance with the invention by providing a memory cell having a floating gate with lateral edges which are aligned directly above edges of the active area in the substrate, a control gate positioned directly above the floating gate, and a select gate spaced laterally from the control gate. The floating gate has a bottom wall and side walls which face corresponding walls of the control gate in capacitive coupling relationship, with the height of the side walls being on the order of 80 to 160 percent of the width of the bottom wall. In some embodiments, the floating gate is wider than the overlying control gate and has projecting portions which overlie the source and drain regions of the stack transistor. In all the embodiments, the memory cells can be biased and operated in page-erasable (or sector-erasable) flash memory mode and bit-erasable (or byte-erasable) EEPROM mode. This makes these memory cells very useful in embedded applications where they can be integrated as the flash memory array and the EEPROM array, and merged in the same die.
The memory cell with the control gate self-aligned with the underlying floating gate is fabricated by forming a poly-1 layer and an overlying dielectric film on a substrate in areas in which the stack transistors are to be formed, forming a poly-2 layer over the dielectric film and over areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form control gates for the stack transistors and select gates for the select transistors, removing the poly-1 layer and the dielectric film to form floating gates in areas which are not covered by the control gates, forming the shallow diffusion regions in silicon substrate along one side of the floating gates for the generation of hot carriers during the programming operation, forming the deep diffusion regions in silicon substrate along the other side of the floating gates for electron tunneling during the erase operation, and forming the source and drain regions with lightly doped diffusion (LDD) implantation in the substrate for the select transistors. The memory cells can be operated in either flash memory mode or EEPROM mode by swapping the shallow diffusion region and the deep diffusion region along the two sides of the floating gates. The floating gates are aligned with active areas in the substrate by forming isolation oxide regions which extend above the substrate at the edges of the active areas, and forming the floating gates on the sides of the isolation oxide regions in alignment with the edges of the active areas.
The memory cell in which the control gate is not self-aligned to the underlying floating gate is fabricated by forming a poly-1 layer, removing the poly-1 layer to form the floating gates, forming the shallow diffusion regions in silicon substrate along one side of the floating gates for the generation of hot carriers during the programming operation, depositing and patterning a dielectric film across the floating gates, forming the gate oxide for the select transistors, forming a poly-2 layer over the dielectric film and over the areas of the substrate in which the select transistors are to be formed, patterning the poly-2 layer to form the control gates for the stack transistors and the select gates for the select transistors, forming the deep diffusion regions in silicon substrate along the other side of the floating gates for electron tunneling during the erase operation, and forming the source and drain regions with LDD implantation in the substrate for the select transistors. The memory cells can be operated in either flash memory mode or EEPROM mode by swapping the shallow diffusion region and the deep diffusion region along the two sides of the floating gates.